1. Field of the Invention
The present invention generally relates to data processing systems and, more particularly, to the transmission of data over a serial line or link between two subsystems of a data processing system.
2. Description of the Related Art
Communications networks can provide high bit-rate transport over a shared medium with a serial line or link, such as passive optical networks, cable television networks (fiber, coaxial or hybrid), digital television, and wireless networks. These shared-medium networks typically use time, frequency or code division multiplexing to transport data signals from a central terminal to several remote customer terminals and time division multiple access (TDMA) to transport data signals from the customer terminals to the central terminal. TDMA is characterized by noncontinuous or burst mode data transmission.
Traditional clock and data recovery (“CDR”) methods are provided for communications systems receiving continuous data streams that have enriched spectra at the sampling frequency. CDR is a useful functionality in high-speed transceivers in the art. Such transceivers serve a plurality of applications, e.g., optical communications, backplane data routing, and chip-to-chip interconnects. The data received therein are asynchronous and noisy, thus requiring that a clock be extracted for allowing synchronous operations. The data also need to be retimed so that jitter accumulated during data transmission can be removed.
A phase locked loop (“PLL”) can be used in clock and data recovery in phase tracking for data being transmitted. A phase detector compares the lead or lag of phases between a voltage controlled oscillator (VCO) clock and the input data. The comparison result is filtered by a loop filter for filtering out high frequency noise and data jitter that can adversely affect the stability of the VCO clock. The loop filter outputs a control voltage for the VCO for aligning the rising edges of the input data. When the PLL is locked, the data can be extracted from the phase detector accordingly. The PLL, however, may have problems tracking high frequency phase jitter in high-speed data recovery systems.
In the case of noncontinuous data transmission, i.e., burst mode transmission, multi-rate oversampling with a long preamble may be required for data recovery. Such processing approaches in data transmission are disadvantageous because of their excessive power consumption and inefficient utilization of bandwidth over the communications link. Moreover, conventional CDR methods are not suited for making fast data recovery decisions.
There is thus a general need in the art for a system and method overcoming at least the aforementioned shortcomings in the art. A particular need exists in the art for a system and method overcoming disadvantages with respect to excessive power consumption and inefficient bandwidth use and difficulty in making fast data recovery decisions over a serial communications link.